The present invention relates to a semiconductor memory. Conventionally, various layouts have been considered for semiconductor memories that include a DRAM (dynamic random access memory).
Japanese Patent Laid-Open No. 2007-287794 discloses a semiconductor memory including a first cell contact and a bit line contact (bit contact) formed on the first cell contact, a second cell contact (cell contact) and a storage node contact (capacitor contact) formed on the second cell contact, and a capacitor formed on the storage node contact. In this case, a center position of the storage node contact is offset in a predetermined direction from a center position of the second cell contact and is moved in a direction approaching the first cell contact in the same active area. Accordingly, the disclosure purports that a closest-packed layout of the storage capacitor can be realized and a sufficient HSG (hemispherical grained) obstruction margin can be secured.
Japanese Patent Laid-Open No. 2004-47999 discloses a DRAM cell including first and second storage nodes (capacitor contacts) respectively formed on both ends of a single active area on a semiconductor substrate having first and second MOS transistors. The first and second storage nodes are respectively electrically connected to a first impurity region that acts as a source region of the first MOS transistor and a second impurity region that acts as a source region of the second MOS transistor. The central axes of the first and second storage nodes respectively pass through first and second points that are spaced from center points of the first and second impurity regions by a predetermined distance along a direction parallel to the longitudinal direction of the active area. In this case, the storage nodes (capacitor contacts) are moved by a predetermined distance in a direction perpendicular to the longitudinal direction of the active area (cell). The first and the second storage nodes are also moved in the same direction.
Japanese Patent Laid-Open No. 11-045982 discloses a semiconductor integrated circuit device configured such that an active area enclosed by a field isolation film on a primary face of a semiconductor substrate is linearly formed, and a bit line BL to be connected to a semiconductor region at the center of the active area is also formed linearly. In addition, a contact hole to which the bit line BL is connected, and a contact hole connected to semiconductor regions on both ends of the active area and at which is formed a plug to be connected to an information storage capacitative element, are formed deviated in opposite directions from the center of a y-direction of the active area (an area parallel to a gate line). In this case, the active area is formed so as to extend in a direction approximately parallel to the bit line.
Japanese Patent Laid-Open No. 2002-031883 discloses a method of manufacturing a semiconductor integrated circuit device using a mask pattern formed on a photomask during a design phase so as to be arranged offset in a separating direction from a data line DL so that when transferring through holes onto a pair of contact holes on either side of the data line DL, the through holes are to be connected to the contact holes but not to the data line DL even when an offset of the pair of through holes on either side of the data line DL occurs.
The present inventor has discovered that a semiconductor memory including a DRAM illustrated in the plan view in FIG. 11 and in FIG. 12, which is a cross-sectional view taken along the line D-D′ in FIG. 11, has the following problem. Here, a description will be given using an example where the DRAM has a ¼ pitch-layout structure in which a basic structure made up in units of four bit lines and four gate lines is repetitively arranged.
A semiconductor memory 50 is formed on one face of a substrate 52, and includes an active area 56 separated by an isolation film 54, a bit line 76, a gate line (word line) 98, a bit contact 70, a cell contact 72, a capacitor contact 78, and a capacitor 90. In FIG. 11, the line extending in a longitudinal direction in the diagram is the gate line 98 and the line extending in a horizontal direction in the diagram is the bit line 76. As illustrated in FIG. 12, the capacitor 90 is made up of a lower electrode 92, a capacitance insulating film 94, and an upper electrode 96. In addition, an insulating film 58 is formed on the substrate 52. The bit line 76, the gate line 98 (not illustrated in FIG. 12), the bit contact 70, the cell contact 72, the capacitor contact 78, and the capacitor 90 are formed in the insulating film 58.
The bit contact 70 connects the active area 56 of the substrate 52 with the bit line 76. In addition, the cell contact 72 and the capacitor contact 78 connect the active area 56 of the substrate 52 with the capacitor 90. In this case, the cell contact 72 and the capacitor contact 78 are formed at the same position as seen in planar view with the exception of unintended errors due to processing errors during manufacturing.
Furthermore, the bit line 76 and the capacitor contact 78 are set to be arranged so as not to come into contact with each other even when processing errors during manufacturing are taken into consideration. For example, the capacitor contact 78 is desirably arranged at the center of adjacent bit lines 76 in order to secure an overlapping margin. Moreover, to ensure a connection between the cell contact 72 and the active area 56, the cell contact 72 must be arranged at the center of the active area 56.
Meanwhile, the recent miniaturization of devices has resulted in the density variation in impurity ions in a channel region of a transistor having a greater impact on transistor characteristics. In order to lower the impact of such a density variation, an overlapping region (channel region) of the gate line (word line) 98 making up the gate electrode of the transistor and each active area 56 is preferably made as wide as possible. In order to increase DRAM arrangement density and secure a wide overlapping region of the gate line 98 and each active area 56, the active area 56 is desirably arranged so that a wide angle is formed between the extended direction of the active area 56 and the extended direction of the gate line 98.
FIG. 13 illustrates an example of a plan view of a semiconductor memory 50 configured as described above.
In this case, an angle θa formed by the extended direction of the gate line 98 and the active areas 56 is set wider than an angle θb of the configuration illustrated in FIG. 11. Such an arrangement ensures a wider overlapping region of the gate line 98 and each active area 56 when the intervals of adjacent gate lines 98 and the intervals of adjacent bit lines 76 are respectively set similar to those illustrated in FIG. 11. Accordingly, device characteristics can be improved and stabilized while maintaining DRAM arrangement density.
However, a configuration such as that illustrated in FIG. 13 has a problem in that an overlapping margin of the bit line 76 and the capacitor contact 78 cannot be secured. FIG. 14 is a cross-sectional view taken along line E-E′ in FIG. 13. At the locations indicated by the arrows in the diagram, there is a risk that an insufficient margin between the bit line 76 and the capacitor contact 78 may lead to the bit line 76 coming into contact with the capacitor contact 78 due to processing errors during manufacturing.
The conventional techniques described above are incapable of solving such problems.